UDK 681.3:629.7 Vestnik SibGAU 2014, No. 4(56), P. 132–138
METHOD AND SYSTEM OF ERROR INJECTION FOR TESTING THE FAULT TOLERANCE PROCESSOR ON-THE BOARD CONTROL SYSTEM OF SPACECRAFT
S. A. Chekmaryov
Siberian State Aerospace University named after academician M. F. Reshetnev 31, Krasnoyarsky Rabochy Av., Krasnoyarsk, 660014, Russian Federation E-mail: zaq259@yandex.ru
Error injection method for testing onboard processors’ fault-tolerance is proposed. It is based on the modification of the on-chip debugging method which uses the test port of the processor. Unlike the basic method, error injection is made by a built-in hardware error injector rather than by an external computer. An error injection system architecture is developed for the proposed method. Using the processor test port injection module can read the data with the required address in the internal memory; inject errors by inverting the required bit; write back data with injected errors by the initial address. An implementation example of the proposed system is demonstrated. The procedure of injecting and correcting a single failure in the processor on-chip memory is described. It is shown that the proposed method does not introduce much excessiveness in the core architecture of the processor. As a result of experiments about 90 % of injected errors were detected and at least 92 % of them were corrected. Implementation of the hardware injector provides greater autonomy and realistic testing of the processor’s fault-tolerance.
On-chip debugger, single event upset, fault injection, System on Chip, FPGA.
References
- Yudintsev V. [Radiation hardened integrated circuit reliability in space and on earth]. Elektronnika, Nauka, Tekhnologiya, Biznes. 2007, no. 5, p. 72–77 (In Russ.).
- Osipenko P. [Single event upset – a challenge for modern microprocessors]. Elektronnye komponenty. 2009, no. 7, p. 12–15 (In Russ.).
- Ulimov V. N., Tapero K. I. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh kosmicheskogo primeneniya [Radiation effects in silicon integrated circuits for space application]. Moscow, Binom. Laboratoriya znaniy Publ., 2012, 234 p.
- M.-C. Hsueh, T. K. Tsai, R.K. Iyer. Fault Injection Techniques and Tools. Computer, 1997, p. 75–82.
- Andre V. Fidalgo, Gustavo R. Alves, Jose M. Ferreira, Real Time Fault Injection Using Enhanced OCD – A Performance Analysis, dft, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006, p. 254–264.
- Jiri Gaisler, LEON3-FT-RTAX SEU test results GAISLER RESEARCH, 2005, р. 8.
- Qiang Zhang, Jun Zhou, Xiaozhou Yu A Kind of Low-cost Non-intrusive Autonomous Fault Emulation System. Computer and Information Science. 2011, vol. 4, no. 1, p. 90–99.
- Hanov V. Kh., Vergazov M. Ju., Chekmarev S. A., Shahmatov V. A., Lukin F. A. [The concept of creating an onboard control system for satellites]. Vestnik SibGAU. 2012, no. 5 (45), p. 144–149 (In Russ.).
- Gobchanskij O. [Problems of creation of onboard computing systems on satellites] Sovremennye tehnologii avtomatizacii. 2001, no. 4, p. 28–34 (In Russ.).
- SPARC V8 32-bit Processor LEON3 LEON3-FT Companion Core Data Sheet Template Design Gaisler Research, 2010. p. 41.
- Kozlov-Kononov D. [Family of processor cores Cortex: a combination of high performance and low power consumption]. ELEKTRONIKA: Nauka, Tekhnologiya, Biznes. 2010, no. 8, p. 16–24 (In Russ.).
- Sputniks. Available at: http://www.sputnix.ru/ru/ technologies (accessed: 25.08.2013).
- AMBA Specification rev. 2.0, May 99, IHI 0011A, ARM Ltd. Available at http://www.arm.com (accessed: 25.08.2013).
- GRLIB IP Library User’s Manual. Aeroflex Gaisler. 2010. p. 78.
- M. Y. Hsiao. A Class of Optimal Minimum Odd-Weight-Column SEC-DED Codes. IBM J. Res. Develop. 1970. no 14, p. 395–401.
Chekmaryov Sergey Anatolevich – engineer of Information technology security department, Siberian State Aerospace University named after academician M. F. Reshetnev. E-mail: zaq259@yandex.ru
