Научная электронная библиотека ULRICH'S Periodicals Directory

Сибирский государственный университет
науки и технологий имени академика М.Ф. Решетнева

Сибирский аэрокосмический журнал
ISSN 2712-8970 (Print) ISSN 2782-5760 (on-line)

Сведения об образовательной организации

UDK 681.32
FPGA FUNCTIONAL COMPLETE TOLERANT LOGIC ELEMENTS FOR AEROSPACE COMPUTER SYSTEMS
S. F. Tyurin
Perm National Research Polytechnic University; 29, Komsomolsk Аv., Perm, 614990, Russian Federation
Functional and complete (in the sense of Theorem Post) tolerant elements have been proposed as a paradigm spread structurally stable computers, proposed by Professor V. A. Kharitonov, at the turn of the 90s of the twentieth century, on the register transfer level. Structurally stable computers have the ability to emulate the desired command system in case of failure of individual teams from the original set. In turn, functionally complete tolerant logic elements FCTLE have the ability of maintaining the functional completeness of a given model of failures. In 1996-1997 FСT were obtained function model considering the constant failure of one of the four inputs of the corresponding element (stuck-at-0; stuck-at-1). They were the composition of AND, OR, NOT logic functions. Of these, the practical significance of known functions 2OR-2AND-NOT; 2AND-2OR-NOT. When adding Bridging Faults: (Dominant; Wired AND, OR; Dominant AND / OR), it proved that the cardinality of the set of functions FPT reduced, but 2OR-2ANDNOT; 2AND-2OR-NOT maintain tolerance. Then there were the issues of maintaining the functional completeness at the transistor level – for internal failures logic element (valve) – KMOS transistors (stuck-closed transistor – permanently closed, stuck-open transistor – permanently open. It is shown that the functional completeness is preserved in case of failure of one transistor or a top of the circuit – connect “+” power supply or lower – bus connection “Ground”. Then there is understanding that can be similar to conserve not only the functional completeness, but also the realization of a function at the level of a single element. The article features FCTLE elements included in the FPGA with the so-called LUT (Look Up Table).
Keywords: FPGA, logic functions, logic element, LUT, transistor, redundancy, functional complete tolerant logic element (FCTLE), reliabilities.
References

1. Kharitonov V. A., Tiurin S. F. [Models of sustainability management is functionally redundant systems]. Materialy mezhdunarodnoi nauchno-prakticheskoi konferentsii “Upravlenie bol'shimi sistemami”. [Proceedings of the international scientific-practical conference “Managing large systems”]. Moscow, 1997, P. 266 (In Russ.).

2. Tiurin S. F. [Functionally Complete Tolerant Boolean functions]. Nauka i tekhnologiya v Rossii, 1998, No. 4, P. 7–10 (In Russ.).

3. Tiurin S. F. [Design adaptable to digital equipment failures redundancy of basic functions]. Priborostroenie, 1999, No. 1, P. 36–39 (In Russ.).

4. Tiurin S. F. [Adapting to failures Single source circuits function generator with a functionally-complete tolerance elements]. Priborostroenie, 1999, No. 7, P. 32–34 (In Russ.).

5. Tiurin S. F. [Retention of functional completeness of Boolean functions under “failures” of the arguments]. Avtomatika i telemekhanika, 1999, No. 9, P. 176–186.

6. Tiurin S. F., Grekov A. V., Gromov O. A. [The definition of functional full-tolerant Boolean functions of four arguments in view of the model variables circuits]. Doklady Akademii voennykh nauk. 2011, No. (49), P. 35–44 (In Russ.).

7. Tiurin S. F., Gromov O. A., Grekov A. V. [Functionally full-tolerant element FCT+]. Nauchnotekhnicheskie vedomosti Sankt-Peterburgskogo gosudarstvennogo politekhnicheskogo universiteta, 2011, No. 1(115), P. 24–31 (In Russ.).

8. Ugriumov E. P. Tsifrovaia skhemotekhnika. [Digital circuitry]. St. Petersburg, BKhV-Peterburg Publ., 2004, 518 p.

9. Tiurin S. F., Gromov O. A. Funktsional’no-polnyy tolerantnyy element [Functionally full-tolerant element]. Patent RF, No. 2438234, 2011.

10. Tiurin S. F., Gromov O. A., Grekov A. V. Funktsional’no-polnyy tolerantnyy element. [Functionally full-tolerant element]. Patent RF, No. 2449469, 2012.

11. Tiurin S. F., Gromov O. A., Grekov A. V., Suleimanov A. A. Funktsional’no-polnyy tolerantnyy element. [Functionally full-tolerant element]. Patent RF, No. 2496227, 2013.

12. Dudkin Iu. P., Tiurin S.F., Iuzhakov A. A., Gromov O. A. Funktsional’no-polnyy tolerantnyy element. [Functionally full-tolerant element]. Patent RF, No. 2541854, 2015.

13. Tsybin S. Programmiruemaya kommutatsiya PLIS: vzgliad iznutri. [Programmable switching FPGA Insights]. Available at: http://www.kit-e.ru/articles/plis/2010_11_56.php (accessed: 16.12.2014).

14. Tiurin S. F., Nabatov A. V., Gromov O. A., Grekov A. V., Karlov D. A. Programmiruemoe logicheskoe ustroistvo. [Programmable logic device]. Patent RF, No. 2503993, 2014.

15. Tiurin S. F. Programmiruemoe logicheskoe ustroistvo. [Programmable logic device]. Patent RF, No. 2544750, 2015.

16. Tiurin S. F., Gorodilov A. Iu., Vikhorev R. V. Programmiruemoe logicheskoe ustroistvo. [Programmable logic device]. Patent RF, No. 2547229, 2015.

17. Polozhitel’noe reshenie FSIS RF po zayavke № 2014116999/08(026804)ot 25.04.2014. [The positive decision of the Federal Antimonopoly Service of the Russian Federation from 03.20.15 on request 2014110973/08 on 03/21/2014]. Tiurin S. F., Gorodilov A. Iu., Danilova E. Iu. Programmiruemoe logicheskoe ustroistvo. [Programmable logic device].

18. Dzh. D. Ul’man. Vychislitel’nye aspekty SBIS. [Computational Aspects of VLSI]. Moscow, Radio i sviaz’ Publ., 1990, 480 p.

19. Polozhitel’noe reshenie FSIS RF ot 20.03.15 po zayavke 2014110973/08 ot 21.03.2014. [The positive decision of the Federal Antimonopoly Service of the Russian Federation from 03.20.15 on request 2014110973/08 on 03/21/2014]. Tiurin S. F. Iacheika staticheskoi operativnoi pamyati [SRAM Cell].

20. Zolotukha R., Komolov D. Stratix III – novoe semeistvo FPGA firmy Altera. [Stratix III – a new family of FPGA from Altera]. Available at: http://kit-e.ru/assets/files/pdf/2006_12_30.pdf (accessed: 28.11.2015).

21. Ispol’zovanie resursov PLIS Stratix III firmy Altera pri proektirovanii mikroprotsessornykhy yader. [Resource use of Stratix III FPGA from Altera the design of microprocessor cores]. Available at:file:///C:/Users/%D0%A2%D1%8E%D1%80%D0%B8%D0%BD/Desktop/%D0%A6%D1%8B%D0%B1%D0%B8%D0%BD%2010%20%D0%B3%D0%BE%D0%B4.pdf (accessed: 27.11.2015).

22. Chekmarev S. A. [Method and system for testing the error injection failures resistant processor board system of spacecrafts]. Vestnik SibGAU. 2014, No. 4 (56), P. 132–137 (In Russ.).


Tyurin Sergey Feofentovich – honored inventor of the Russian Federation, Dr. Sc., professor, professor of Department of Automation and Telemechanics, Perm National Research Polytechnic University. E-mail: tyurinsergfeo@yandex.ru.