UDK 004.318
FAULT INJECTION TECHNOLOGY FOR FAULT TOLERANCE TESTING OF MICROPROCESSORS DESIGNED TO ONBOARD EQUIPMENT
S. A. Chekmarev, V. Kh. Khanov, A. S. Timokhovich
Reshetnev Siberian State Aerospace University 31, Krasnoyarsky Rabochy Av., Krasnoyarsk, 660037, Russian Federation
The fault injection process specification and overview of injection methods are presented. The fault injection technology is for fault tolerance testing of computing elements and devices and operating systems used for onboard equipment. The fault injection in microprocessor imitates single event upset of internal and external microprocessor memory. A single event upset consists of a memory cell inverting in value. Injection model is defined by injection planning set included kind of fault, its time and location; by system-under-test operation set during injection; by injection result set: parried fault or not; also by statistical measure set derived from results. The process of fault injection in microprocessor consists of memory cell inverting by any methods during microprocessor operation. Injection results are collected and then processed by external computer to microprocessor under test. Injection methods are physical or realized in system-under-test model which can be invasive or non-invasive. Physical methods are based on using of real process which may cause faults in factual microprocessor system. Non-invasive methods do not use or minimally use the hardware interference in microprocessor system-under-test for injection. Most of the injection methods are common for any electronic mostly digital system, but two methods are specifically developed for microprocessor systems: software fault injection and injection via the testing port using the on-chip-debugger. Injection via testing port injects the fault independent of microprocessor program execution. Most of fault injection methods based on the on-chip-debugger use external hardware-in-the-loop environment what slow down the injection process. The developed method of on-chip injection is targeting on SoC-microprocessors. In this method the injection infrastructure is immediately within testing microprocessor as IP-core what minimizes time delays. Overview shows fault injection technology has the high practical significance and brisk growth.
Keywords: fault tolerance of microprocessor, fault injection model, fault injection methods, on-chip-debugger injection, on-chip fault injection.
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